On August 24th, STMicroelectronics and the National University of Singapore (NUS) announced the launch of the ST-NUS HELIX enterprise laboratory. This 

is a four-year research project, officially known as "Hardware for Embodied Low-power Intelligent Xcceleration" (Hardware for embodied low-power intelligent 

acceleration), aiming to develop the next-generation hardware for generative and edge-edge AI. The project is supported by the Singapore Research, 

Innovation and Enterprise 2025 Program (RIE2025), and is located in the Design and Engineering College and the Computing College of the National University

 of Singapore. The research scope covers AI algorithms, system architectures, heterogeneous accelerators, on-chip memory hierarchies, circuit design, and 

chip integration into silicon implementation.

The technical roadmap of this project points to a clear issue: The energy consumption bottleneck of edge AI mainly comes from data transfer, rather than 

arithmetic operations themselves. For embodied devices such as robots, humanoid robots, and drones, they need to complete perception, computation, and

 execution in real time under compact power and volume constraints. The repeated transfer of model weights and intermediate data between the processor 

and off-chip memory will consume a lot of energy and introduce latency. Therefore, the focus of HELIX research is on storage-centric architectures, innovative 

in-memory computing, and scalable memory-storage co-processing systems, aiming to move storage closer to computation and even complete some 

operations within the storage structure. ST provides the project with a dedicated design chassis based on its proprietary P18 process (18nm fully depleted 

silicon-on-insulator, FD-SOI) and embedded phase-change memory (ePCM), as an industrial-grade research platform. P18 FD-SOI supports ultra-low power 

operation and adaptive body bias, while ePCM, together with the on-chip SRAM hierarchy, provides high-density non-volatile storage, and the combination 

of these two technologies can significantly reduce the off-chip data traffic that dominates the energy consumption of memory-based AI workloads.

For semiconductor manufacturers, the value of such university-industry laboratories lies in verifying architectural ideas on industrial processes in advance. 

Laurent Malier, Executive Vice President of Global Technology R&D at ST, stated that ST's advantage as an IDM is to be able to combine advanced silicon 

technology, embedded storage, circuit design, heterogeneous integration, and chiplet capabilities. The expected output of HELIX is a research platform and 

prototype demonstrations, rather than immediately commercial processor series - an accelerator concept that performs well in software or FPGA simulations,

 when mapped to a specific process node, will face multiple limitations such as storage density, interconnect latency, leakage, analog constraints, and real 

power supply. The laboratory exposes these weaknesses in advance.

The efficiency competition of edge AI is shifting from computing power figures to the design choices of storage and data paths. On the same device, CPU, 

neural network accelerators, DSP, embedded non-volatile storage, SRAM, and interfaces need to coexist. Process and packaging solutions will re-determine 

the computing architecture and software collaboration methods. The combination of FD-SOI and ePCM represents a different option from the mainstream 

FinFET plus HBM route: exchanging lower power consumption and on-chip non-volatile density for shorter power supply distance and lower standby power 

consumption, suitable for battery-powered, highly real-time embodied devices. ST makes this base open for universities for verification and also gives the 

FD-SOI process platform a new ecological entry point in the era of edge AI.