Microchip has released a new XpressConnect series of signal relay chips, namely PM8691 XpressConnect RTM-C 16xG6. It is compatible with both PCIe 6.0 and CXL 3.1 protocols, and is used to address the high-speed signal integrity issues within AI computing clusters and high-performance computer rooms, thereby extending the transmission distance of high-speed signals. 

The challenges in signal transmission in high-speed interconnection scenarios 

The AI data center is equipped with a large number of CPU and GPU parallel computing nodes. The overall performance of the system not only depends on the computing power of the chips, but also is limited by the signal transmission distance and the rising edge delay. 

The single channel speed of PCIe 6.0 reaches 64GT/s. It adopts PAM4 four-level modulation, doubling the data transmission volume under the same clock. The signal needs to pass through multiple layers of paths including the motherboard, adapter board, and external cables. Different wiring lengths will cause signal timing deviations. Issues such as multiple clock domains, long-line impedance, and inductance-capacitance mismatch can also occur, which may lead to signal distortion.

Without a signal relay chip for compensation, the transmission loss and timing deviation will directly reduce the link speed, and even cause data transmission errors. 

The core function of the signal relay chip 

PM8691 integrates signal buffering, timing synchronization, and waveform restoration functions. It is placed between the sender and receiver of the signal to complete three basic processing tasks: compensating for the delay caused by long-distance transmission, eliminating signal jitter, reorganizing the signal eye diagram, and amplifying the signal amplitude.

This chip is suitable for enterprise-level servers and can optimize the link stability of NVMe flash arrays, CXL memory expansion areas, and PCIe switching architectures. 

PM8691 Key Parameters and Compatibility 

Link latency: The total latency between pins is less than 12ns, which is only 20% of the upper limit allowed by the PCIe 6.0 specification, thereby reducing the data waiting and error correction overhead in large-scale computing clusters. 

2. Protocol Compatibility: Native support for PCIe 6.0 and CXL 3.1, backward compatible with PCIe 3.0/4.0/5.0 and CXL 3.0; 

3. Channel Configuration: Supports x4/x8/x16 channel splitting. It can automatically identify port directions and supports channel reversal and polarity inversion. 

4. Hardware simplification: Built-in bypass capacitors are used to reduce the number of peripheral components on the circuit board and simplify the wiring design. 

Complementary products and development and debugging solutions 

PM8691 belongs to the complete server product line of Microchip. The same series also includes switching chips, RAID controllers, host bus adapters, and NVMe control chips.

The chip can be connected to the Microchip ChipLink diagnostic tool. The graphical interface can output 2D eye diagrams and visual waveforms of PAM4 four-layer signals in real time, facilitating the troubleshooting of link faults. 

This signal relay chip adopts industry-standard packaging and can directly replace competing products of the same specification, reducing the single-supplier dependency of data center equipment manufacturers. It also supports hot swapping and end-to-end data integrity verification, and is suitable for standardized server batch design.