TSMC unveiled its general manufacturing technology roadmap for the period up to 2029 at its 2026 North American Technology Conference. The advanced manufacturing processes are still advancing. It is notable that TSMC has not rushed to incorporate High-NA EUV (High Numerical Aperture Extreme Ultraviolet) lithography technology into the mass production nodes before 2029. In contrast, Intel introduced High-NA equipment earlier. The real difference between the two companies is not just the choice of equipment, but the trade-offs in terms of production schedule, cost, and yield risk. 

In recent years, TSMC's AI and HPC (High Performance Computing) businesses have surpassed its mobile phone business. This is reflected in its roadmap - TSMC plans advanced manufacturing processes based on the market demands of end devices in a "segmented" manner, rather than a "one-size-fits-all" approach. Specifically: nodes such as A16 and A12, which are targeted at AI/HPC, offer significant performance improvements to support technology migration, and their costs are relatively less sensitive, but the update cycle is once every two years; processes such as N2, N2P, N2U, A14, and A13 are mainly targeted at smartphones and client devices. These markets place greater emphasis on cost, energy efficiency, and IP reuse, and have high requirements for design compatibility, maintaining an annual new node update pace. 

· Node A16 has been set for 2027 (slightly delayed compared to the previous 2026), based on the first-generation GAA nanosheet transistors, with SPR back-side power supply introduced, specifically designed for high-performance data center applications; and A16 will be succeeded by A12, expected to be launched in 2029. 

· The A14 process is based on the second-generation GAA nanosheet transistors and provides higher design flexibility through NanoFlex Pro technology. It is expected to be used in high-end smartphones and client chips in 2028. The A13, on the other hand, achieves additional efficiency improvements with minimal disruption, while maintaining the complete design rules and electrical compatibility. Compared to A14, it achieves approximately 6% area reduction. 

Meanwhile, TSMC is continuously expanding the 2nm platform through N2U, and is expected to start production in 2028. N2U takes advantage of the mature process and high yield performance of the N2 technology platform, and can cover AI/HPC and mobile applications at a lower migration cost. 

Why does TSMC now be actively exploring the potential of its existing EUV technology? 

Regarding the latest technologies showcased, TSMC plans to continue advancing the node by optimizing the existing Low-NA EUV system rather than switching to the new High-NA EUV equipment. Zhang Xiaqiang, Senior Vice President of Global Business and Deputy Chief Operating Officer of TSMC, said, "We will introduce High-NA EUV only when it can bring tangible and quantifiable technological gains. At present, with the existing EUV equipment, the A14 and subsequent processes can still achieve significant performance upgrades. The R&D team is continuously exploring the potential of the existing EUV equipment and relying on process optimization to continue the micro-miniaturization advantage of Moore's Law." 

Currently, the global demand for AI computing power has surged, and major manufacturers are accelerating the construction of new wafer factories for expansion. The introduction of High-NA EUV technology also represents a significant capital expenditure: Market reports indicate that the cost of each Low-NA EUV TwinScan NXE: 3800E is approximately $235 million, while the expected cost of each High-NA EUV TwinScan EXE: 5200B is $380 million. 

TSMC's current public roadmap indicates that the nodes planned for 2029 will still not rely on High-NA EUV. They have chosen to continue using the existing EUV lithography machines to complete the research and development and mass production of new-generation optimized processes such as A12 and A13. This is in stark contrast to Intel's approach. It should be noted that High-NA EUV equipment is not the only key factor determining success or failure in the future. Process integration and advanced packaging are also crucial. For example, last year TSMC successfully achieved an increase in the critical dimension and graphic accuracy of advanced processes while reducing defect density by adjusting photoresist materials and mask processes. 

Intel entered the High-NA EUV debugging stage earlier. 

As early as the end of 2023, ASML delivered the first set of High-NA EUV lithography machines to Intel, with the model being TWINSCAN EXE:5000. Intel used it as a test machine and completed its installation at the Fab D1X wafer factory in Oregon, USA, in early 2024. Subsequently, this wafer factory became the semiconductor research and development base of Intel, further developing advanced processes based on High-NA EUV lithography technology. 

The High-NA EUV lithography machine differs significantly from the standard EUV lithography machine. It requires a considerable amount of time to correct the infrastructure and improve the usage experience. Installing the equipment earlier means that Intel can enter the equipment debugging, process integration, and measurement verification stages earlier. However, whether the initial investment of the High-NA can be converted into commercial returns depends on equipment utilization, yield improvement, and the introduction of external customers. 

In lithography equipment, NA represents the numerical aperture, which indicates the ability of the optical system to collect and focus light. High-NA EUV has increased the NA from 0.33 to 0.55. The stronger focusing ability means that it can handle more intricate geometries, and this is also one of the routes for further advancing semiconductor process evolution. 

ASML claims that its High-NA EUV system has achieved an 8nm resolution in a single exposure, which is an improvement compared to the 13.5nm resolution of current Low-NA EUV tools. Although Low-NA EUV systems can also achieve 8nm resolution through dual patterning (double exposure), this method would increase process complexity and affect yield. Therefore, Intel's early adoption of High-NA is regarded as an important technological bet for its advancement in 14A and foundry business. 

David Zinsner, the Chief Financial Officer of Intel, stated at the Citi 2025 Global TMT Conference that the next-generation Intel 14A manufacturing process technology will utilize ASML's latest second-generation High-NA EUV lithography machine, TWINSCAN EXE:5200B. According to the data previously disclosed by Intel, compared to Intel 18A, Intel 14A will achieve a 15-20% increase in performance per watt, a 30% increase in density, and a 25-35% reduction in power consumption. 

If the 14A process can proceed as planned and gain external customer adoption, Intel may leverage its High-NA experience to attract AI/HPC customers. It must be noted that everything is still in the testing of chips and evaluation stage at present, and the external customers adopting the 14A chip have not been fully determined yet. The decision window for potential customers/contract manufacturers will open in the second half of 2026 and continue until the beginning of 2027. 

Although some analysis institutions have raised doubts that by delaying the introduction of High-NA EUV to the mass production stage, Taiwan Semiconductor Manufacturing Company (TSMC) might be at a disadvantage in future competition. However, considering the high cost of High-NA EUV equipment and the fact that there is still room for optimization of the existing EUV equipment, TSMC chose to carefully assess the investment timing. This is more like a choice of pace between technological benefits, equipment costs, and production risks. 

The advanced manufacturing process ultimately needs to focus on yield and customer adoption. 

The competition between Samsung and TSMC has widened after the 7nm technology. Due to the fact that Samsung's performance in the key indicator of transistor density has never surpassed that of TSMC. Although there is already a significant gap in market share between the two, Samsung has not given up its goal of surpassing TSMC. Instead, it has accelerated the development of wafer foundry technology. 

Samsung was the first to adopt the GAA architecture in the 3nm process, and it was the only company to do so in this process. It aimed to gain an advantage over TSMC's FinFET technology through technological gap, but its production performance and customer adoption did not help it overtake TSMC. 

The introduction of the new transistor structure will simultaneously bring about issues such as equipment adaptation, process integration, design rules, and yield improvement. It is not just about the initial launch. A Samsung technology executive once stated: "We underestimated the industrialization difficulty of the GAA process. The complexity of equipment adaptation and process integration was far greater than expected." 

The case of Samsung's 3nm GAA technology demonstrates that advanced structures can only be transformed into competitiveness when they are simultaneously integrated with mass production yield, customer adoption, and cost control. TSMC continues to use the FinFET architecture in its 3nm process, but has maintained the production pace by relying on more mature process integration and customer ecosystem. 

Advanced process competition is not about the one who replaces the equipment first winning. High-NA EUV will become an important tool, but equipment, photoresist, reticle, design rules, yield, advanced packaging, customer introduction and production capacity rhythm must all be in place together. Only when the technology is leading can it become the leading in mass production.